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datasheet 2-output very low power pcie gen1/2/3 clock generator 9fgv0241 idt? 2-output very low power pcie gen1/2/3 clock generator 1 9fgv0241 october 18, 2016 description the 9fgv0241 is a 2-output very low power frequency generator for pcie gen 1, 2 and 3 applications with integrated output terminations providing zo=100 ? . the device has 2 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. recommended application pcie gen1/2/3 clock generator output features ? 2 - 0.7v low-power hcsl-compatible (lp-hcsl) dif pairs w/zo=100 ? ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3 compliant ? ref phase jitter is <1.5ps rms features/benefits ? integrated terminations provide 100 ? differential zo; reduced component count and board space ? 1.8v operation; reduced power consumption ? oe# pins; support dif power management ? lp-hcsl differential clock outputs; reduced power and board space ? programmable slew rate for each output; allows tuning for various line lengths ? programmable output amplitude; allows tuning for various application environments ? dif outputs blocked until pll is locked; clean system start-up ? selectable 0%, -0.25% or -0.5% spread on dif outputs; reduces emi ? external 25mhz crystal; supports tight ppm with 0 ppm synthesis error ? configuration can be accomplished with strapping pins; smbus interface not required for device control ? 3.3v tolerant smbus inte rface works with legacy controllers ? space saving 24-pin 4x4 mm vfqfpn; minimal board space block diagram xin/clkin_25 x2 vss_en_tri ^ckpwrgd_pd# sdata_3.3 ref voe(1:0)# sclk_3.3 vsadr dif0 dif1 2 idt 603-25-150ja4c or 603-25-150ja4i 25mhz ssc capable pll control logic
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 2 9fgv0241 october 18, 2016 pin configuration smbus address selection table power management table power connections gndxtal vss_en_tri ^ckpwrgd_pd# gnd vdd1.8 voe1# 24 23 22 21 20 19 x1_25 1 18 dif1# x2 2 17 dif1 vddxtal1.8 3 16 vdda1.8 vsadr/ref1.8 4 15 gnda gndref 5 14 dif0# gnddig 613dif0 7 8 9 10 11 12 vdddig1.8 sclk_3.3 sdata_3.3 gnd vdd1.8 voe0# v prefix indicates internal 120kohm pull down resistor 9fgv0241 connect epad to gnd 24-pin vfqfpn, 4x4 mm, 0.5mm pitch ^ prefix indicates internal 120kohm pull up resistor sadr address 0 1101000 1 1101010 state of sadr on first application of ckpwrgd_pd# + read/write bit x x true o/p comp. o/p 0 x low low hi-z 1 1 1 running running running 1 0 low low low ckpwrgd_pd# smbus oe bit difx 1. ref is hi-z until the 1st assertion of ckpwrgd_pd# high. after this, when ckpwrg_pd# is low, ref is low. ref pin number vdd gnd 35,24 76 11,20 10,21 16 15 pll analog description xtal, ref digital power dif outputs
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 3 9fgv0241 october 18, 2016 pin descriptions pin# pin name type pin description 1 x1_25 in crystal input, nominally 25.00mhz. 2 x2 out crystal output. 3 vddxtal1.8 pwr power supply for xtal, nominal 1.8v 4 vsadr/ref1.8 latched i/o latch to select smbus address/1.8v lvcmos copy of x1 pin. 5 gndref gnd ground pin for the ref outputs. 6 gnddig gnd ground pin for digital circuitry 7 vdddig1.8 pwr 1.8v digital power (dirty power) 8 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 9 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 10 gnd gnd ground pin. 11 vdd1.8 pwr power supply, nominal 1.8v 12 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 13 dif0 out differential true clock output 14 dif0# out differential complementary clock output 15 gnda gnd ground pin for the pll core. 16 vdda1.8 pwr 1.8v power for the pll core. 17 dif1 out differential true clock output 18 dif1# out differential complementary clock output 19 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 20 vdd1.8 pwr power supply, nominal 1.8v 21 gnd gnd ground pin. 22 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 23 vss_en_tri latched in latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, m = -0.25%, 0 = spread off 24 gndxtal gnd gnd for xtal
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 4 9fgv0241 october 18, 2016 test loads alternate terminations rs rs low-power hcsl differential output test load 2pf 2pf 5 inches zo=100ohm device ref output 33 ref output test load 5pf zo = 50 ohms rs device rs zo driving lvds cc cc r7a r7b r8a r8b 3.3v lvds clock input driving lvds inputs with the 9fgv 0241 receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component value note
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 5 9fgv0241 october 18, 2016 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9fgv0241. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operati on of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affe ct product reliability. electrical parameters are guar anteed only over the recommended operating temperature range. electrical characterist ics?current consumption electrical characteristics? output duty cycle, jitter , and skew characteristics parameter symbol conditions min typ max units notes 1.8v supply voltage vddxx applies to all vdd pins -0.5 2.5 v 1,2 input voltage v in -0.5 v dd +0.3v v 1, 3 input high voltage, smbus v ihsmb smbus clock and data pins 3.6v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.5v. ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddaop vdda, pll mode, all outputs active @100mhz 7 8 ma 1 i ddop vdd, all outputs active @100mhz 15 18 ma 1 suspend supply current i ddsusp vddxxx, pd# = 0, wake-on-lan enabled 6 8 ma 1 powerdown current i ddpd pd#=0 0.6 1 ma 1, 2 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 assumin g ref is not runnin g in power down state operating supply current ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes duty cycle t d c measured differentially, pll mode 45 50 55 % 1 skew, output to output t sk3 v t = 50% 34 50 ps 1 jitter, cycle to cycle t jcyc-cyc pll mode 14 50 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 6 9fgv0241 october 18, 2016 electrical characteristics?input/supp ly/common parameters ?normal operating conditions ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes 1.8v supply voltage vdd supply voltage for core, analog and single-ended lvcmos outputs 1.7 1.8 1.9 v 1 t com commmercial range 0 25 70 c 1 t ind industrial range -40 25 85 c 1 input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v 1 input mid voltage v im single-ended tri-level inputs ('_tri' suffix, if present) 0.4 v dd 0.6 v dd v1 input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v1 schmitt trigger postive goin g threshold volta g e v t+ single-ended inputs, where indicated 0.4 v dd 0.7 v dd v1 schmitt trigger negative going threshold voltage v t- single-ended inputs, where indicated 0.1 v dd 0.4 v dd v1 hysteresis voltage v h v t+ - v t- 0.1 v dd 0.4 v dd v1 output high voltage v ih single-ended outputs, except smbus. i oh = -2ma v dd -0.45 v 1 output low voltage v il single-ended outputs, except smbus. i ol = -2ma 0.45 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 input frequency f in xtal, or x1 input 23 25 27 mhz 1 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.4 1.8 ms 1,2 ss modulation frequency f mod allowable frequency (triangular modulation) 31 31.6 32 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 123clocks1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 1,2 trise t r rise time of single-ended control inputs 5 ns 1,2 smbus input low voltage v ilsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 0.8 v 1,4 smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 5 for v ddsmb < 3.3v 2.1 3.6 v 1,5 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 1.7 3.6 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. capacitance 3 time from deassertion until outputs are >200 mv 4 for v ddsmb < 3.3v, v ilsmb <= 0.35v ddsmb input current 5 for v ddsmb < 3.3v, v ihsmb >= 0.65v ddsmb ambient operating temperature
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 7 9fgv0241 october 18, 2016 electrical characteristics?dif 0.7v low power hcsl outputs electrical characteristi cs?phase jitter parameters ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes scope avera g in g on 3.0v/ns settin g 23.14.3 v/ns 1, 2, 3 scope avera g in g on 2.0v/ns settin g 1.5 2.3 3.5 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 3 20 % 1,2,4 voltage high v hi gh 660 794 850 1,7 voltage low v low -150 21 150 1 max voltage vmax 816 1150 1 min voltage vmin -300 -15 1 vswing vswing scope averaging off 300 1551 mv 1,2 crossin g volta g e (abs) vcross_abs scope avera g in g off 300 397 550 mv 1,5 crossing voltage (var) -vcross scope averaging off 15 140 mv 1,6 2 measured from differential waveform 7 at default smbus settings. measurement on single ended signal using absolute value. (scope averaging off) mv 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). slew rate trf 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting ? -vcross to be smaller than vcross absolute. 1 guaranteed by design and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv ta = t com or t ind; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jphpcieg1 pcie gen 1 202535 86 ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz 0.8 0.9 1.1 3 ps (rms) 1,2,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 1.5 1.6 1.9 3.1 ps (rms) 1,2,5 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.33 0.37 0.50 1 ps (rms) 1,2,4,5 1 guaranteed by design and characterization, not 100% tested in production. 5 applies to all differential outputs 4 calculated from intel-supplied clock jitter tool phase jitter, pci express t jphpcieg2 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12.
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 8 9fgv0241 october 18, 2016 electrical characteristics?ref clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs wi th -0.5% spread spectrum enabled ta = t com or t ind ; supply voltage per vdd of normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values ppm 1,2 clock period t p eriod 25 mhz output nominal 40 ns 1,2 rise/fall slew rate t rf1 byte 3 = 1f, v oh = vdd-0.45v, v ol = 0.45v 0.5 1 2.5 v/ns 1,3 rise/fall slew rate t rf1 byte 3 = 5f, v oh = vdd-0.45v, v ol = 0.45v 0.5 1.6 2.5 v/ns 1,3 rise/fall slew rate t rf1 byte 3 = 9f, v oh = vdd-0.45v, v ol = 0.45v 0.5 2 2.5 v/ns 1,3 rise/fall slew rate t rf1 byte 3 = df, v oh = vdd-0.45v, v ol = 0.45v 0.5 2.1 2.5 v/ns 1,3 duty cycle d t1 v t = vdd/2 v 45 53.1 55 % 1,4 duty cycle distortion d tcd v t = vdd/2 v 0 2 4 % 1,5 jitter, cycle to cycle t j c y c-c y c v t = vdd/2 v 19 250 ps 1,4 noise floor t j dbc1k 1khz offset -130 -105 dbc 1,4 noise floor t j dbc10k 10khz offset to nyquist -140 -120 dbc 1,4 jitter, phase t jphref 12khz to 5mhz 0.63 1.5 ps (rms) 1,4 1 guaranteed by design and characterization, not 100% tested in production. 3 typical value occurs when ref slew rate is set to default value 4 when driven by a crystal. 5 when driven by an external oscillator via the x1 pin. x2 should be floatin g in this case. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is trimmed to 25.00 mhz 0 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 notes measurement wi ndow units ssc off center freq. mhz 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max dif 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is trimmed to 25.00 mhz measurement wi ndow units ssc on center freq. mhz notes
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 9 9fgv0241 october 18, 2016 general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: read/write address is determined by sadr latch. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 10 9fgv0241 october 18, 2016 smbus table: output enable register byte 0 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 1 bit 2 dif oe1 output enable rw low/low enabled 1 bit 1 dif oe0 output enable rw low/low enabled 1 bit 0 1 smbus table: ss readback and vhigh control register byte 1 name control function type 0 1 default bit 7 ssenrb1 ss enable readback bit1 r latch bit 6 ssenrb1 ss enable readback bit0 r latch bit 5 ssen_swcntrl enable sw control of ss rw ss control locked values in b1[4:3] control ss amount. 0 bit 4 ssensw1 ss enable software ctl bit1 rw 1 0 bit 3 ssensw0 ss enable software ctl bit0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01 = 0.7v 1 bit 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 1 bit 2 slewratesel dif1 adjust slew rate of dif1 rw 2.0v/ns 3.0v/ns 1 bit 1 slewratesel dif0 adjust slew rate of dif0 rw 2.0v/ns 3.0v/ns 1 bit 0 1 smbus table: ref control register byte 3 name control function type 0 1 default bit 7 rw 00 = slowest 01 = slow 0 bit 6 rw 10 = fast 11 = faster 1 bit 5 ref power down function wake-on-lan enable for ref rw ref does not run in power down ref runs in power down 0 bit 4 ref oe ref output enable rw low enabled 1 bit 3 1 bit 2 1 bit 1 1 bit 0 1 byte 4 is reserved and reads back 'hff'. reserved reserved slew rate control 00' = ss off, '01' = -0.25% ss, '10' = reserved, '11'= -0.5% ss 00' for ss_en_tri = 0, '01' for ss_en_tri = 'm', '11 for ss_en_tri = '1' ref reserved controls output amplitude reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 11 9fgv0241 october 18, 2016 recommended crystal charac teristics (3225 package) smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 0 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 0 bit 2 device id2 r 0 bit 1 device id1 r 1 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 a rev = 0000 byte count programming writing to this register will configure how many bytes will be read back, default is = 8 bytes. device type revision id reserved 0001 = idt 00010 binary or 02 hex 00 = fgv, 01 = dbv, 10 = dmv, 11= reserved device id reserved vendor id reserved parameter value units notes frequency 25 mhz 1 resonance mode fundamental - 1 frequency tolerance @ 25c 20 ppm max 1 frequency stability, ref @ 25c over operating temperature range 20 ppm max 1 temperature range (commerical) 0~70 c 1 temperature range (industrial) -40~85 c 2 equivalent series resistance (esr) 50 ? 5 ppm max 1 notes: 1. fox 603-25-150. 2. for i-temp, fox 603-25-261.
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 12 9fgv0241 october 18, 2016 thermal characteristics marking diagrams notes: 1. ?lot? is the lot number. 2. ?yyww? is the last two digits of the year and week that the part was assembled. 3. ?l? denotes rohs compliant package. 4. ?i? denotes industrial temperature grade. parameter symbol conditions pkg typ value units notes c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 38 c/w 1 1 epad soldered to board thermal resistance nlg20 nlg24 lot 241al yyww lot 241ail yyww
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 13 9fgv0241 october 18, 2016 package outline and package dimensions (nlg24) ordering information "lf" suffix to the part numb er are the pb-free configurat ion and are rohs compliant. ?a? is the device revision d esignator (will not correlate with the datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperatur e range, high reliability, or other extr aordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitr y or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. millimeters symbol min max a 0.80 1.00 a1 0 0.05 a3 0.25 reference b 0.18 0.30 e 0.50 basic d x e basic 4.00 x 4.00 d2 min./max. 2.3 2.55 e2 min./max. 2.3 2.55 l min./max. 0.30 0.50 n24 n d 6 n e 6 anvil singulation -- or -- sawn singulation n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2 part / order number shipping packaging package temperature 9fgv0241aklf tubes 24-pin vfqfpn 0 to +70 c 9fgv0241aklft tape and reel 24-pin vfqfpn 0 to +70 c 9fgv0241akilf tubes 24-pin vfqfpn -40 to +85 c 9fgv0241akilft tape and reel 24-pin vfqfpn -40 to +85 c
9fgv0241 2-output very low power pcie gen1/2/3 clock generator idt? 2-output very low power pcie gen1/2/3 clock generator 14 9fgv0241 october 18, 2016 revision history rev. issue date intiator description page # a 8/15/2012 rdw 1. changed description, recommended application and ds title to say "clock generator" instead of "frequency generator" 2. changed output features text. updated block diagram to highlight internal terminations. 3. highlighted the standby power pins in the pinout (pins 4,5,8) 4. added footnote 1 to power management table 5. cleaned up the test load diagrams and merged with alternate terminations diagram. 6. updated electrical tables with char data, removed "clock periods- single-ended outputs" table which was redundant. updated footnote two on clock periods table. 7. changed integration range for phase jitter calculation of ref from "12khz to 20mhz" to "12khz to 5mhz" 8. corrected byte 6 9. added thermal data and recommended crystal tables 10. move to final. 1,2,4,5- 8,11-13 b 12/19/2012 at 1. added sadr column to smbus address selection table. 2. changed vih min. from 0.65*vdd to 0.75*vdd, vim min. from 0.35*vdd to 0.4*vdd and max. from 0.65*vdd to 0.6*vdd, and vil max. from 0.35*vdd to 0.25*vdd 2,6 c 7/24/2103 rdw 1. minor updates to electrical characterisitcs per additional char data. 2. idd reduced for 9fgv0241 3. slew rate parameters for each setting for ref output added to table. 4. typical values updated. 5. changed descriptions of byte 3, bits 7:6 to "slowest, slow, fast, faster, since actual values are now included in the ref electrical table. 5-8,10 d 9/10/2014 rdw updated ordering information/shipping pacakging from "trays" to "tubes". 13 e 2/3/2015 rdw updated iddaop and iddop typ and max specs per latest characterization review. 5 f 11/30/2015 rdw updated block diagram 1 g 1/4/2016 rdw corrected typo in ordering information; changed rev "b" to rev "a" 13 h 10/18/2016 rdw removed idt crystal part number
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